**Structural Model : Half Adder**

module half_adder(

output S,C,

input A,B

);

xor(S,A,B);

and(C,A,B);

endmodule

**Structural**

**Model : Full Adder**

module full_adder(

output S,Cout,

input A,B,Cin

);

wire s1,c1,c2;

half_adder HA1(s1,c1,A,B);

half_adder HA2(S,c2,s1,Cin);

or OG1(Cout,c1,c2);

endmodule

**Structural**

**Model : 4 Bit Ripple Carry Adder**

module ripple_adder_4bit(

output [3:0] Sum,

output Cout,

input [3:0] A,B,

input Cin

);

wire c1,c2,c3;

full_adder FA1(Sum[0],c1,A[0],B[0],Cin),

FA2(Sum[1],c2,A[1],B[1],c1),

FA3(Sum[2],c3,A[2],B[2],c2),

FA4(Sum[3],Cout,A[3],B[3],c3);

endmodule

**Test Bench : 4 Bit Ripple Carry Adder**

module test_ripple_adder_4bit;

// Inputs

reg [3:0] A;

reg [3:0] B;

reg Cin;

// Outputs

wire [3:0] Sum;

wire Cout;

// Instantiate the Unit Under Test (UUT)

ripple_adder_4bit uut (

.Sum(Sum),

.Cout(Cout),

.A(A),

.B(B),

.Cin(Cin)

);

initial begin

// Initialize Inputs

A = 0;

B = 0;

Cin = 0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

A=4'b0001;B=4'b0000;Cin=1'b0;

#10 A=4'b1010;B=4'b0011;Cin=1'b0;

#10 A=4'b1101;B=4'b1010;Cin=1'b1;

end

initial begin

$monitor("time=",$time,, "A=%b B=%b Cin=%b : Sum=%b Cout=%b",A,B,Cin,Sum,Cout);

end

endmodule

Is "Sum" from the top level 4bit_Ripple_Carry_Adder module supposed to be "set equal" to anything?

ReplyDelete"4bit_Ripple_Carry_Adder" is a hardware module which has two 3-bit input buses(A,B), an input line(Cin), a 3-bit output bus(Sum) and an output line (Cout).

DeleteYes, obviously Sum is supposed to be connected to the module which requires the sum of A and B.

hey jaya...i need one favour i am implementing this paper for my project http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=5337888 but in this they have used radix 2 but i am going to use radix 4 and they have implemented in CMOS i am going to do gate level implementation .....yes i need verilog code and test bench for radix 4 modified booth algorith 8 bit , then i need code for hybrid carry save adder tree ....i this paper i couldnt understand the process in that CSA and accumulator can u explain it to me pl...i have to complete this project in one month...pl help me wth this project ..

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ReplyDeleteCould you elaborate the errors. (Error description, line no etc...)

DeleteThanks for replying! i got it figured out. It wasn't a problem with your code.

DeleteThanks for replying! i got it figured out. It wasn't a problem with your code.

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ReplyDeletethanks alot

ReplyDeleteHi there, can i have the verilog for "ripple-carry adder and 4-bit block carry skip adder". Please help me, mail me to puvan5555@gmail.com

ReplyDeleteThis comment has been removed by the author.

ReplyDeleteThis comment has been removed by the author.

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