Pseudo Random Sequence Generator in Verilog

Pseudo Random Sequence is widely used in spread spectrum communication, to spread and de-spread the information sequence. The following diagram shows a PN sequence generator which has 3 memory elements, leads to processing gain 7 (2^3 - 1). According to the diagram, if the initial state is all zero, then the sequence will also be all zeros which is not usable.

Behavioural Model

module PNSeqGen(
    input clk, reset,
    output s3
    );
reg s1, s2, s3;
wire s0;
// MODULO 2 ADDITION
assign s0 = s1 ^ s3;
// STATE MACHINE
always @ (posedge clk or reset) begin
// INITIAL STATE SHOULDN'T BE 000 => 100
if(reset) begin
s1 <= 1;
s2 <= 0;
s3 <= 0;
end else begin
s1 <= s0;
s2 <= s1;
s3 <= s2;
end
end
endmodule

Test Bench

`timescale 1ns / 1ps
module Test_PNSeqGen;
// Inputs
reg clk;
reg reset;
// Outputs
wire s3;
// Instantiate the Unit Under Test (UUT)
PNSeqGen uut (
.clk(clk), 
.reset(reset), 
.s3(s3)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#10 reset = 1;
#10 reset = 0;
#200 $finish;
end
always begin
#5 clk = ~clk;
end
// PRINT SEQUENCE
always @ (posedge clk) $write("%b",s3);      
endmodule

Output

001110100111010011101